The present invention is related to integrated circuit output buffers and, more particularly, to output buffer circuits for reducing noise.
An output buffer is a common circuit found in integrated circuits. These circuits are used to drive signals from the integrated circuit to the external environment. Typically in a MOS integrated circuit, the output buffer circuit is formed by a pair of large drive transistors serially connected between the first power supply, at V.sub.CC, which is higher than the second power supply, typically at ground. The common source/drain connection between the two drive transistors forms the output terminal of the buffer circuit. The gates of the two drive transistors are typically connected to some logic so that signals are generated on the gates of the drive transistors in response to a logic signal at an input terminal of the buffer circuit. In this manner, one, or the other. of the drive transistors is turned on and the other off so that a logic high or logic low signal is created at the output terminal. Sometimes the logic circuit has a control terminal to turn the buffer circuit off and on. Such a typical output buffer circuit is shown in FIG. 1.
However, buffer circuits typically have a problem with noise generated by the switching of the drive transistors. This noise is generated on the power supply buses when the drive transistors turn off and on. Typically an integrated circuit has several buffer circuits connected parallel at the periphery of an integrated circuit die. Typically, the noise is defined by .DELTA.V=L(dI/dt) where L is a total inductance of the respective power buses on the integrated circuit and (dI/dt) is the instantaneous change in current through the power bus.
These generated noises can often be very large to create various problems, including the misinterpretation of the logic state of a digital signal. The present invention is an output buffer circuit which lowers the generation of noise in a circuit arrangement which does not occupy very much valuable integrated circuit space.